1. Field of the Invention
The present invention relates to the field of integrated circuit (IC). More specifically, the present invention relates to crossbar devices, and their usage in reconfigurable circuits.
2. Background Information
Crossbar devices for programmatically connecting n inputs to m outputs, in general, are known in the art.
FIGS. 1a-1b show a basic implementation of a pass n-mos crossbar device known in the art. Input lines 100 are connectable to output lines 101 through switches 102. Each switch 102 comprises a n-mos pass transistor 103 with its source connected to one input line and its drain connected to one output line; and a memory element 104 controlling the gate of pass transistor 103. Connection between one input line and one output line is effectuated by applying a high voltage (by storing a 1 in the memory element) to the gate of the corresponding pass transistor; putting the pass transistor in a low resistance state between its source and drain. Output buffer 105 amplifies and regenerates the voltage level on the output line, restoring the pass transistor 103 threshold voltage (Vth) drop. The configuration of such a crossbar should connect only one input to one output, otherwise it can possibly create a short circuit between two inputs connected to the same output. This type of crossbar causes problems at power up if the memory element is unknown, possibly connecting several inputs to a same output. Also, this type of crossbar needs n×m memory elements to realize a n inputs to m outputs crossbar.
FIG. 2 shows another prior art implementation (U.S. Pat. No. 6,289,494) having a more efficient structure. This type of crossbar needs (n/4)×m memory elements 201 and m 2 to 4 decoders 202 to realize a n inputs to m outputs crossbar. For a large crossbar input number the penalty of the 2 to 4 decoder 202 is compensated by the reduction in the number of memory elements required. One problem with this architecture is the capacitive loading of the input lines. To connect input line 203a to output line 204 a 1 is programmed into memory element 201a, and the decoder drives a 1 on its output 205b. Therefore, input line 203b is connected to capacitor 206. Similarly, every fourth input of one column is connected to a capacitor 206. Note, the capacitive load of one input depends on the programming pattern of the other inputs, which could ends up with a high capacitive load on some input lines and a low capacitive load on some other input lines. Also, the capacitance 206 is pretty big because it represents the parasitic load of five n-mos drains/sources and the metal interconnections between these five n-mos drains/sources.
FIG. 3 shows another prior art implementation (U.S. Pat. No. 5,260,610). This type of crossbar also needs (n/2)×m memory elements 301 plus m memory elements 302. To connect input line 303a to output line 304 we must program a 1 in memory element 301 and a 1 in memory element 302. But, by programming a one in memory element 301, input line 303b is connected to capacitance 306. Capacitance 306 is large because it represents the parasitic load of half of the pass transistor of one column plus the metal interconnection between them. If the crossbar has 32 inputs, then capacitance 306 includes the parasitic load of 16 n-mos drains/sources. Again, the capacitive loading of one input line can vary dramatically with the programming pattern of the other inputs.
In applications where a significant number of crossbars are employed and interconnected, such as reconfigurable circuit applications, the input capacitive load variation of one crossbar input with respect to the programming pattern fits other inputs makes the timing optimization of high performance devices very difficult. Additionally, these and other prior art crossbar devices are found to consume more power and/or area than desired, as well as contributing to current swing.
Thus, a crossbar device and techniques of employment in reconfigurable circuit without at least some of these disadvantages are desired.